1. Field of the Invention
The present invention relates to a phase locked loop. More particularly, it relates to architecture for a digital phase locked loop frequency synthesizer which is capable of both small frequency channels and fast settling time.
2. Background of Related Art
A phased locked loop (PLL) is a device which is capable of outputting a synthesized frequency locked to an input master frequency signal. A conventional Phase Locked Loop (PLL) frequency synthesizer is a circuit which generates (synthesizes) an output signal whose frequency is a rational multiple of the known, stable input master frequency signal.
Conventionally, there is a fundamental tradeoff in conventional PLL frequency synthesizer design between channel spacing (frequency control) and settling time. The primary parameter involved in this tradeoff is the reference frequency or update rate of a phase detector used in the PLL.
A block diagram of a conventional PLL frequency synthesis is shown in FIG. 3.
In FIG. 3, a conventional digital PLL comprises a master clock 302 generating a master frequency signal fMASTER. A reference frequency divider 304 divides the master clock signal fMASTER by an integer value R.
A phase detector 306, a charge pump 308, and a loop filter 310 provide a voltage signal to a voltage controlled oscillator (VCO) to cause a voltage controlled oscillator (VCO) 312 to output a particular frequency signal.
A VCO frequency divider 314 is placed in a feedback loop between the output of the VCO 312 and one input to the phase detector 306. The VCO frequency divider 314 divides by an integer value X.
The PLL forms a control loop which, when locked, forces the phase difference of the two signals applied to the phase detector to zero. Two signals whose phases are lockedxe2x80x94either to a zero offset or some constant offsetxe2x80x94are also equal in frequency.
In particular, the PLL takes as an input a stable master frequency signal frequency fMASTER generated by, e.g., a master oscillator 302. The input master frequency signal fMASTER is divided by the reference frequency divider 304, which typically is a programmable down-counter, to provide a reference signal with frequency fREF shown in Equation (2) below:       f    REF    =            1      R        ⁢          f      MASTER      
The reference frequency signal fREF is applied to one input of the phase detector 306.
The output of the frequency synthesizer is taken from the VCO 312. The VCO 312 is tunable over a range of frequencies, for uses such as when tuning the channels of an FM radio, or when selecting any of a plurality of different channels over which a cordless telephone operates.
The output signal from the VCO 312 is divided to what is ideally the reference frequency fREF by the programmable frequency divider 314. (The VCO frequency divider 314 is embodied as an asynchronous divider, a synchronous down-counter, or a combination of the two for frequencies greater than 100 MHz such as in a dual modulus pre-scaler or divider followed by one or more down-counters.)
The divided output signal is fed back to a second input of the phase detector 306.
Thus, the output of the R and X dividers are applied to the phase detector, which, along with the charge pump, generates an error signal proportional to the difference in phase between the two inputs.
The loop filter is a lowpass filter critical in settling phase noise and settling time of the loop.
In operation, the synthesized output frequency of the VCO 312 can be changed simply by reprogramming the division factor of the feedback VCO divider 314.
The phase detector error is zero when the X and R outputs are identical in phase (and therefore also frequency). Accordingly, the output frequency signal from the VCO 312 will be X times the reference frequency fREF, with X being an integer.
When the PLL is locked, the input to the phase detector is also at the reference frequency fREF, as shown in Equation (3) below:       f    REF    =            1      X        ⁢          f      VCO      
Solving Equations (2) and (3) for the frequency signal fVCO output from the VCO 312 provides Equation (4) shown below:       f    VCO    =            X      R        ⁢          f      MASTER      
The phase detector 306 and the charge pump 308 provide an output frequency signal which is proportional to the phase error between its two inputs, i.e., the reference frequency signal fREF and the fedback VCO divided frequency signal. In response, the phase detector 306 generates an error signal whose duration is proportional to the delay between rising edges of its two inputs, i.e., between the reference frequency fREF and the fedback VCO divided signal.
The charge pump 308 functions like a pulse width modulated current digital-to-analog converter (DAC), modulated by the duration of the output of the phase detector 306.
The loop filter 310 is a lowpass filter, which integrates the current output from the charge pump 308 to become the control voltage signal applied to control the VCO 312. Generally, loop filter design impacts loop stability, phase noise, and settling time.
Fast settling time is of particular importance in systems where channels must be scanned during acquisition, and in frequency-hopped spread spectrum (FHSS) systems in particular. Unfortunately, settling time is inversely related to loop bandwidth, and thus loop bandwidth should typically be at least an order of magnitude lower than the reference frequency fREF to reduce spurious emissions produced by the reference frequency fREF and its harmonics.
Since the synthesized output frequency signal fVCO is an integer multiple of the reference frequency fREF in a typical frequency synthesizer, the minimum tuning increment of the VCO 312 is equal to the reference frequency fREF. Thus, it follows that channel spacing must be some integer multiple of the reference frequency fREF. In other words, the maximum value of the reference frequency fREF for a particular system is the channel spacing, and in many cases is a sub-harmonic of the channel spacing. Thus, channel spacing plays an important part in determining loop bandwidth and settling time.
In particular, in conventional PLL designs, the frequency output from the VCO 312 must be an integer multiple of the reference frequency fREF. The result is that the smallest possible tuning increment or channel spacing is equal to the reference frequency fREF, the second smallest possible tuning increment is equal to twice the reference frequency fREF, etc.
When changing the output frequency from the PLL frequency synthesizer, i.e., when changing channels, it is most desirable that the PLL settle in on the new frequency as quickly as possible, i.e., as small a PLL settling time as possible is desired. However, because of the conventional tradeoff between reference frequency and settling time, some amount of settling time must be endured to accommodate a desired resolution in the output frequency based on the choice of reference frequency.
Low settling time is particularly attractive in portable, battery powered applications, where, for instance, scanning for an open channel or waiting for the PLL to settle when coming out of a sleep mode can be responsible for a significant portion of the standby current consumption. In such a system, to have many possible frequency channels, a lower reference frequency is required. Alternatively, to provide for a faster settling time, a higher reference frequency is required. The designer typically predetermines the value of the reference frequency based on a desired value of the settling time.
There is a need for a PLL design which allows for both smaller frequency channels and fast settling time regardless of the value of the reference frequency.
In accordance with the principles of the present invention, a digital phase locked loop comprises a phase detector receiving at a first input a representation of an input frequency signal, and a voltage controlled oscillator. A numerically controlled oscillator is in a feedback loop between an output of the voltage controlled oscillator and a second input to the phase detector. The numerically controlled oscillator forms a frequency divider.
A method of providing feedback between an output signal of a voltage controlled oscillator and an input signal to a phase detector in a digital phase locked loop in accordance with another aspect of the present invention comprises dividing the output signal from the voltage controlled oscillator with a numerically controlled oscillator, and providing the divided output signal to the input of the phase detector.